Methodology Labs

Our recent projects have been on FPGA implementations using Altera and Xilinx FPGAs, at client sites. Some of which are now in production. We have a few active projects nearing completion.

Verification of all these projects were achieved using industry standard simulators such as Questasim and Modelsim using full System Verilog language support and UVM as required.

Design was completed in system verilog place and route tools of Xilinx and Altera were used.

Engineers are familiar with Vivado HLS.

Our focus has always been to adopt latest tools in Design and Verification, while working with Clients.

Establishing a suite of regression tests covering all functional aspect of an FPGA/ASIC is our strategy. Exploring valid scenarios to break the design under test accelerates the process of finding bugs.

We also offer training for individuals and corporations, in Verification and/or Design by taking them through a series of lectures and labs giving a real feel of the industry.